DS3105LN+【PDF 3/124 页】IC TIMING LINE CARD 64-LQFP

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Sheet目录1994

1页 2页 [3页]4页 5页 6页 7页

DS3105

100

FSCR1

Frame-Sync Configuration Register 1

7Ah

Bit #

Name

—

SYNCSRC[2:0]

8KINV

8KPUL

2KINV

2KPUL

Default

Bits 6 to 4: SYNC12 Source (SYNCSRC[2:0]). When external frame sync is configured for SYNC123 mode, this

field specifies the input clocks to associate with the SYNC1 and SYNC2 pins. SYNC3 is always associated with

input clock IC9 in this mode. See Section 7.9.1.

0XX = SYNC1 pin associated with IC3 or IC5, SYNC2 pin associated with IC4 or IC6

1X0 = SYNC1 pin associated with IC3, SYNC2 pin associated with IC4

1X1 = SYNC1 pin associated with IC5, SYNC2 pin associated with IC6

Bit 3: 8kHz Invert (8KINV). When this bit is set to 1 the 8kHz signal on clock output FSYNC is inverted. See

Section 7.8.2.5.

0 = FSYNC not inverted

1 = FSYNC inverted

Bit 2: 8kHz Pulse (8KPUL). When this bit is set to 1, the 8kHz signal on clock output FSYNC is pulsed rather than

50% duty cycle. In this mode output clock OC3 must be enabled, and the pulse width of FSYNC is equal to the

clock period of OC3. See Section 7.8.2.5.

0 = FSYNC not pulsed; 50% duty cycle

1 = FSYNC pulsed, with pulse width equal to OC3 period

Bit 1: 2kHz Invert (2KINV). When this bit is set to 1 the 2kHz signal on clock output MFSYNC is inverted. See

Section 7.8.2.5.

0 = MFSYNC not inverted

1 = MFSYNC inverted

Bit 0: 2kHz Pulse (2KPUL). When this bit is set to 1, the 2kHz signal on clock output MFSYNC is pulsed rather

than 50% duty cycle. In this mode output clock OC3 must be enabled, and the pulse width of MFSYNC is equal to

the clock period of OC3. See Section 7.8.2.5.

0 = MFSYNC not pulsed; 50% duty cycle

1 = MFSYNC pulsed, with pulse width equal to OC3 period

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